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| zeddii_home | RP: acked. I’ll spawn a build for beaglebone-yocto, qemuarm and the mpc on 4.14 | 00:05 |
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| mithro | RP: So, I think I'm about to accidently reinvent bitbake / yocto but I haven't been able to find the time to test using bitbake for our FPGA based soft-CPU SoCs.... | 00:34 |
| mithro | RP: Any chance you know someone who might have time to whip together a bitbake / yocto proof of concept? | 00:37 |
| mithro | If I could get to a stage were I had proof that what I wanted to do would work under bitbake / yocto it would give me the push needed to investigate it myself | 00:39 |
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| fitzsim | mithro: I've used this before: https://github.com/nathanrossi/meta-hdl | 01:24 |
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| mithro | fitzsim: Do you have an example of how to use that? | 01:26 |
| fitzsim | mithro: with that layer I've successfully built FPGA bit files for the Lattice iCE40-HX8K | 01:26 |
| fitzsim | I wrote a recipe for the bit file (Verilog source) and running bitbake on that recipe built the entire FPGA toolchain native, then build the bit file | 01:27 |
| fitzsim | not sure if that's the sort of thing you're looking for | 01:27 |
| fitzsim | *built the bit file | 01:27 |
| mithro | fitzsim: Potentially - except I need a couple of steps in front of that to get to the verilog stage... | 01:28 |
| fitzsim | KO | 01:28 |
| fitzsim | OK | 01:28 |
| mithro | fitzsim: And a couple of steps after that to generate the code which would run on the fpga's SoftCPU | 01:28 |
| fitzsim | are you using a proprietary FPGA toolchain? | 01:28 |
| mithro | fitzsim: In most cases, but just adding support for the open tools | 01:28 |
| mithro | fitzsim: https://github.com/timvideos/litex-buildenv | 01:29 |
| mithro | fitzsim: And https://docs.google.com/document/d/1V47Zc0eyjUUGBNsJuYORdb4TqH4C1WjzrX9odX0YdZE/edit is the doc were it feels like we are about to reinvent bitbake / OE | 01:30 |
| fitzsim | oh, Migen, I think I've seen that | 01:30 |
| fitzsim | is that the Python based HDL toolchain? | 01:30 |
| mithro | fitzsim: One of them (there is also MyHDL and a few others) | 01:30 |
| fitzsim | yeah, very interesting project | 01:31 |
| mithro | fitzsim: We also support a *bunch* of boards / configurations - see https://travis-ci.org/timvideos/litex-buildenv/builds/425975970 | 01:31 |
| fitzsim | the stuff to generate code for the FPGA's SoftCPU, Yocto is definitely perfect for | 01:33 |
| fitzsim | assuming a cross GCC toolchain, for example | 01:33 |
| mithro | fitzsim: Specially since we are starting to get Linux and Zephyr support for running on the SoftCPUs | 01:33 |
| fitzsim | you can also generate SDKs so that users of the SoftCPU, so that they don't have to build everything, they can start from a self-extracting shell script | 01:34 |
| * mithro use to contribute to bitbake back when it was just really doing OpenZarus stuffd :-P | 01:34 | |
| fitzsim | *for users | 01:34 |
| mithro | Apparently some of my code scarelly might still be in use inside bitbake - RP was poking me about it a year or two ago.... | 01:35 |
| fitzsim | nice | 01:35 |
| mithro | But I haven't really done anything with bitbake for 10+ years... | 01:35 |
| fitzsim | the Verilog generator stuff is probably doable too, but you might have to write some classes | 01:36 |
| fitzsim | I haven't used any "point at an external proprietary toolchain" features of Yocto | 01:37 |
| mithro | fitzsim: I would love some help proving it out if you have some experience in this area -- I also know that there are layers floating around for things like RISC-V and external FPGA proprietary toolchain stuff... | 01:37 |
| mithro | fitzsim: Proving the openflow works here would also be super helpful | 01:38 |
| mithro | fitzsim: I also work on https://symbiflow.github.io/ in my spare time :-) | 01:38 |
| fitzsim | mithro: e.g., iverilog in your requirements document is already packaged in meta-hdl | 01:39 |
| mithro | Using the vendor tools makes me sad :-P | 01:40 |
| mithro | fitzsim: we also provide pre-built FPGA gateware for people who don't want to install the vendor tools and are happy to not modify the soc | 01:44 |
| fitzsim | yeah, makes sense | 01:45 |
| fitzsim | yeah, it was on bunnie's blog that I read about this before, re-reading... | 01:45 |
| fitzsim | mithro: does LiteX target a Lattice iCE40 today, and are there good non-trivial example projects for it? | 01:49 |
| fitzsim | mithro: oh yeah, SymbiFlow, I read about that on Clifford Wolf Twitter feed | 01:50 |
| fitzsim | mithro: that's a really exciting one, in that it might be able to target Xilinx FPGAs too | 01:51 |
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| mithro | fitzsim: cr1901_modern in the #timvideos channel is in the process of sending pull requests at this exact moment | 01:53 |
| mithro | (ice40 support in litex-buildenv for the tinyfpga-b2) | 01:54 |
| mithro | Gah | 01:54 |
| mithro | tinyfpga-bx | 01:54 |
| mithro | Then I'll add support for a bunch of other ice40 based boards | 01:54 |
| mithro | The main reason is for fupy.github.io support | 01:55 |
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| mithro | MicroPython for firmware on a soft-CPU based SoC generated from Python! :-) | 01:55 |
| mithro | Python all the things! | 01:56 |
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| mithro | fitzsim: more info at https://j.mp/fupy2018 around recent stuff... | 01:59 |
| mithro | Phone is going flat so might disappear for a bit as I finish walking home... | 01:59 |
| mithro | Lightning talk I gave at pycon au a week or two ago | 02:01 |
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| yocti | New news from stackoverflow: How to enable dbus-X11 in the yocto <https://stackoverflow.com/questions/52231808/how-to-enable-dbus-x11-in-the-yocto> | 04:05 |
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| jdel | how does a task dependency on another recipe's do_populate_sysroot task work? | 05:07 |
| jdel | is do_prepare_recipe_sysroot required to be exceuted for those to actually take effect in a build? | 05:07 |
| jdel | (ie if your tasks never run do_prepare_recipe_sysroot, the files gleaned from <other package>:do_populate_sysroot never make it to your recipe-sysroot dir) | 05:08 |
| jdel | i'm trying to chase down an issue with a class where RDEPS are not being determined properly when restoring from sstate | 05:09 |
| jdel | but package_qa catches it and throws an error | 05:10 |
| jdel | but if I cleanall and remake no error ( and pkgdata/runtime/foo actually changes to include RDEPS lines after that rebuild) | 05:10 |
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| jdel | ugh I figured it out | 05:52 |
| jdel | do_package_qa has the dependency of ${POPULATESYSROOTDEPS} | 05:52 |
| jdel | while do_package does not | 05:52 |
| jdel | but do_package's shlibs function won't work without binutils | 05:52 |
| jdel | so do_package doesn't add the RDEPS it should, then do_package_qa comes along, plops the sysroot into place, and calls the same binaries succesfully | 05:53 |
| jdel | this is compounded by the fact that "deploy" build runs do_populate_sysroot, which (when not run from setscene) also populates ${POPULATESYSROOTDEPS} | 05:53 |
| jdel | s/populates/depends on/ | 05:53 |
| jdel | so it would *only* fail when do_package was being run not from setscene, but populate_sysroot was | 05:54 |
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| nrossi | mithro: litex/migen is on my list of tools to try out, and on the list to add to meta-hdl :). Wanted to get the nextpnr-ecp5 going first though | 08:00 |
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| mithro | hey nrossi | 18:25 |
| mithro | hi jdel | 18:25 |
| mithro | opps wrong channel | 18:25 |
| mithro | nrossi: You should join us on #timvideos channel | 18:25 |
| mithro | nrossi / fitzsim: I send people free hardware btw :-) | 18:26 |
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| mithro | nrossi / fitzsim: If you happen to be around, I would love some help getting started with that fpga overlay? | 22:56 |
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| mithro | nrossi / fitzsim: Putting my notes here -> https://docs.google.com/document/d/1hBvcE83vDRn5EVzcv4Qv_dcGlDuXp5pNI-_yzrEOwxs/edit#heading=h.w74uc35et1g3 | 23:04 |
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