Saturday, 2018-09-08

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zeddii_homeRP: acked. I’ll spawn a build for beaglebone-yocto, qemuarm and the mpc on 4.1400:05
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mithroRP: So, I think I'm about to accidently reinvent bitbake / yocto but I haven't been able to find the time to test using bitbake for our FPGA based soft-CPU SoCs....00:34
mithroRP: Any chance you know someone who might have time to whip together a bitbake / yocto proof of concept?00:37
mithroIf I could get to a stage were I had proof that what I wanted to do would work under bitbake / yocto it would give me the push needed to investigate it myself00:39
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fitzsimmithro: I've used this before:
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mithrofitzsim: Do you have an example of how to use that?01:26
fitzsimmithro: with that layer I've successfully built FPGA bit files for the Lattice iCE40-HX8K01:26
fitzsimI wrote a recipe for the bit file (Verilog source) and running bitbake on that recipe built the entire FPGA toolchain native, then build the bit file01:27
fitzsimnot sure if that's the sort of thing you're looking for01:27
fitzsim*built the bit file01:27
mithrofitzsim: Potentially - except I need a couple of steps in front of that to get to the verilog stage...01:28
mithrofitzsim: And a couple of steps after that to generate the code which would run on the fpga's SoftCPU01:28
fitzsimare you using a proprietary FPGA toolchain?01:28
mithrofitzsim: In most cases, but just adding support for the open tools01:28
mithrofitzsim: And is the doc were it feels like we are about to reinvent bitbake / OE01:30
fitzsimoh, Migen, I think I've seen that01:30
fitzsimis that the Python based HDL toolchain?01:30
mithrofitzsim: One of them (there is also MyHDL and a few others)01:30
fitzsimyeah, very interesting project01:31
mithrofitzsim: We also support a *bunch* of boards / configurations - see
fitzsimthe stuff to generate code for the FPGA's SoftCPU, Yocto is definitely perfect for01:33
fitzsimassuming a cross GCC toolchain, for example01:33
mithrofitzsim: Specially since we are starting to get Linux and Zephyr support for running on the SoftCPUs01:33
fitzsimyou can also generate SDKs so that users of the SoftCPU, so that they don't have to build everything, they can start from a self-extracting shell script01:34
* mithro use to contribute to bitbake back when it was just really doing OpenZarus stuffd :-P01:34
fitzsim*for users01:34
mithroApparently some of my code scarelly might still be in use inside bitbake - RP was poking me about it a year or two ago....01:35
mithroBut I haven't really done anything with bitbake for 10+ years...01:35
fitzsimthe Verilog generator stuff is probably doable too, but you might have to write some classes01:36
fitzsimI haven't used any "point at an external proprietary toolchain" features of Yocto01:37
mithrofitzsim: I would love some help proving it out if you have some experience in this area -- I also know that there are layers floating around for things like RISC-V and external FPGA proprietary toolchain stuff...01:37
mithrofitzsim: Proving the openflow works here would also be super helpful01:38
mithrofitzsim: I also work on in my spare time :-)01:38
fitzsimmithro: e.g., iverilog in your requirements document is already packaged in meta-hdl01:39
mithroUsing the vendor tools makes me sad :-P01:40
mithrofitzsim: we also provide pre-built FPGA gateware for people who don't want to install the vendor tools and are happy to not modify the soc01:44
fitzsimyeah, makes sense01:45
fitzsimyeah, it was on bunnie's blog that I read about this before, re-reading...01:45
fitzsimmithro: does LiteX target a Lattice iCE40 today, and are there good non-trivial example projects for it?01:49
fitzsimmithro: oh yeah, SymbiFlow, I read about that on Clifford Wolf Twitter feed01:50
fitzsimmithro: that's a really exciting one, in that it might be able to target Xilinx FPGAs too01:51
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mithrofitzsim: cr1901_modern in the #timvideos channel is in the process of sending pull requests at this exact moment01:53
mithro(ice40 support in litex-buildenv for the tinyfpga-b2)01:54
mithroThen I'll add support for a bunch of other ice40 based boards01:54
mithroThe main reason is for support01:55
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mithroMicroPython for firmware on a soft-CPU based SoC generated from Python! :-)01:55
mithroPython all the things!01:56
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mithrofitzsim: more info at around recent stuff...01:59
mithroPhone is going flat so might disappear for a bit as I finish walking home...01:59
mithroLightning talk I gave at pycon au a week or two ago02:01
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yoctiNew news from stackoverflow: How to enable dbus-X11 in the yocto <>04:05
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jdelhow does a task dependency on another recipe's do_populate_sysroot task work?05:07
jdelis do_prepare_recipe_sysroot required to be exceuted for those to actually take effect in a build?05:07
jdel(ie if your tasks never run do_prepare_recipe_sysroot, the files gleaned from <other package>:do_populate_sysroot never make it to your recipe-sysroot dir)05:08
jdeli'm trying to chase down an issue with a class where RDEPS are not being determined properly when restoring from sstate05:09
jdelbut package_qa catches it and throws an error05:10
jdelbut if I cleanall and remake no error ( and pkgdata/runtime/foo actually changes to include RDEPS lines after that rebuild)05:10
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jdelugh I figured it out05:52
jdeldo_package_qa has the dependency of ${POPULATESYSROOTDEPS}05:52
jdelwhile do_package does not05:52
jdelbut do_package's shlibs function won't work without binutils05:52
jdelso do_package doesn't add the RDEPS it should, then do_package_qa comes along, plops the sysroot into place, and calls the same binaries succesfully05:53
jdelthis is compounded by the fact that "deploy" build runs do_populate_sysroot, which (when not run from setscene) also populates ${POPULATESYSROOTDEPS}05:53
jdels/populates/depends on/05:53
jdelso it would *only* fail when do_package was being run not from setscene, but populate_sysroot was05:54
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nrossimithro: litex/migen is on my list of tools to try out, and on the list to add to meta-hdl :). Wanted to get the nextpnr-ecp5 going first though08:00
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mithrohey nrossi18:25
mithrohi jdel18:25
mithroopps wrong channel18:25
mithronrossi: You should join us on #timvideos channel18:25
mithronrossi / fitzsim: I send people free hardware btw :-)18:26
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mithronrossi / fitzsim: If you happen to be around, I would love some help getting started with that fpga overlay?22:56
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mithronrossi / fitzsim: Putting my notes here ->
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